1. Field of the Invention
The present invention generally relates to timing analysis methods and apparatuses, programs and storage media, and more particularly to a timing analysis method and a timing analysis apparatus for evaluating a performance of an integrated circuit when designing the integrated circuit such as an LSI, and to a computer-readable program and a computer-readable storage medium for causing a computer to carry out a timing analysis according to such a timing analysis method.
2. Description of the Related Art
According to the conventional timing analysis method employed in CAD or the like, the timing analysis is carried out by taking into consideration the worst case conditions of the delay times of all of the gates forming the integrated circuit that is to be designed. For example, if a macro cell A and a macro cell B forming the integrated circuit are connected, the macro cell A has an average delay time tA and a standard deviation σA, and the macro cell B has an average delay time tB and a standard deviation σB, a minimum worst case condition Min is represented by Min=tA+tB−3(σA+σB), and a maximum worst case condition Max is represented by Max=tA+tB+3(σA+σB).
By carrying out the timing analysis by taking into consideration the worst case conditions, it is possible to guarantee the operation of the integrated circuit.
A Japanese Laid-Open Patent Application No. 2002-279012 proposes a circuit evaluation method that calculates a delay distribution of an integrated circuit by taking into consideration a correlation relationship of the performances of wirings or elements of the integrated circuit.
However, when the timing analysis is always carried out by taking into consideration the worst case conditions of the delay times of the gates, it is necessary to set the operating margin of the gates to an extremely large value, and the operating margin of the integrated circuit that is finally designed becomes unnecessarily large. As a result, there were problems in that the degree of freedom of design of the integrated circuit deteriorates due to the unnecessarily large operating margin, and that the cost of the integrated circuit becomes high.